The present invention relates to a video signal transmission apparatus for transmitting a multi-bit, digital, video signal converted to a serial signal.
For example, the technique of converting a multi-bit, digital, video signal into a serial signal and transmitting the same has been used in the trunk communications, LAN (Local Area Network), etc.
When transmitting a digital signal in this way, the transmitter multiplies the synchronization signal contained in a multi-bit digital signal, that is, the clock signal, to generate a clock signal for transmission of serial signal and multiplexes the multi-bit digital signal to generate a serial signal.
Further, the receiver uses a clock signal extracted from a frequency component contained in the received serial signals using a PLL (Phase Locked Loop) circuit so as to demultiplex the serial signal.
Here, the clock signal for transmission of the serial signal has a considerably high frequency compared with the clock signal of the multi-bit digital signal. For this reason, in order to reduce the transmission error, it is necessary to use a transmission clock signal of a low jitter having a high tire precision.
Accordingly for the transmitter, for example, a low jitter high precision clock signal output from a crystal oscillator is used as the clock signal of the multi-bit digital signal serving as the base for generating the transmission clock.
A liquid crystal display or other display receiving as its input a digital signal, however, sometimes is serially sent an R, G, and B multi-bit digital video signal.
Such a digital video signal is comprised by a 12- to 24-bit digital signal indicating a color gradation and SYNC (synchronization) signal indicating a synchronization position of an image. These digital signal and SYNC signal are synchronous with a dot clock signal. The color gradation of one pixel, an element comprising the image, is indicted for every dot clock signal.
Here, the frequency of the dot clock signal is set to about 25 to 70 MHz in accordance with the total number of pixels of the image.
The above-mentioned digital video signal is generally generated by a large-sized LSI (large scale integrated circuit) referred to as a graphic accelerator. The dot clock signal generated by the graphic accelerator contains a phase modulation component in addition to a pure synchronization clock component for the following reasons (1) and (2).
(1) In the graphic accelerator, the clock signal from the crystal oscillator is transformed in frequency by the PLL circuit, but an unnecessary and harmful signal component, that is, spurious noise, leaks out of this PLL circuit. This spurious noise appears as the phase modulation component of the dot clock signal.
(2) The noise accompanying a large volume of digital signal processing handled by the graphic accelerator leaks to the dot clock. For example, in the transmission of a R, G, and B digital video signal, the period for transmitting the data to be actually displayed as the image and a blanking period for not performing the image display are repeated with a cycle of the horizontal synchronization signal. For this reason, a strong phase modulation comprised of the frequency of the horizontal synchronization signal as a component is contained in the dot clock signal.
For this reason, the dot clock signal, the phase modulation component is mainly distributed at positions of a fraction to a multiple of the frequency of the horizontal synchronization signal.
However, there is a problem that if such a phase modulation component is contained in the dot clock signal, an obstacle occurs in the serial transmission of the digital video signal and the digital video signals cannot be correctly transmitted.
An object of the present invention is to provide a video signal transmission apparatus capable of suppressing the influence exerted upon the transmission clock signal by strong phase modulation having mainly the frequency of the horizontal synchronization signal as its component and, thereby, correctly transmitting the digital video signal.
The video signal transmission apparatus according to a first aspect of the present invention comprises a first PLL circuit having a first cutoff frequency lower than a frequency of a horizontal synchronization signal contained in a digital video signal, having the characteristics of causing attenuation of a phase modulation component of a frequency higher than the first cutoff frequency, and generating a first transmission clock signal of a frequency of N (integer of 2 or more) times a first dot clock signal for identifying one pixel""s worth of data of the digital video signal and phase locked looped to the first dot clock signal; a first conversion means for generating a serial signal from a plurality of a parallel input element signals comprising the digital video signal based on the first dot clock signal and the first transmission clock signal; a transmission channel for transmitting the serial signal; a second PLL circuit having a second cutoff frequency higher than the frequency of the horizontal synchronization signal, tracking the phase modulation of a frequency lower than the second cutoff frequency, and generating a second transmission clock signal from the serial signal input via the transmission channel; a frequency division circuit for dividing the second transmission clock signal 1/N to generate a second dot clock signal; and, a second conversion means for generating a plurality of element signals to be output in parallel form a serial signal input though the transmission channel based on the second dot clock signal and the second transmission clock signal.
Preferably, the fist PLL circuit attenuates a phase modulation component contained in the first dot clock signal more than higher the frequency in a frequency region higher than the first cutoff frequency.
More preferably, the second PLL circuit has less of a tracking error the lower the frequency in a frequency region lower than the second cutoff frequency.
Further, the plurality of element signals are digital color signals and a synchronization signal
Further, preferably, N is 4, 18, 24, 28, 30, or 32.
Further, according to a second aspect of the present invention, there is provided a video signal transmission apparatus for generating and transmitting a serial signal from a plurality of parallel input element signals comprising a digital video signal, comprising a PLL circuit having a cutoff frequency lower than a frequency of a horizontal synchronization signal contained in the digital video signal, having the characteristic of causing attenuation of a phase modulation component of a frequency higher than the cutoff frequency, and generating a transmission clock signal of a frequency of N (integer of 2 or more) times a dot clock signal for identifying one pixel""s worth of data of the digital video signal and phase locked looped to the dot clock signal and a conversion means for generating a serial signal from a plurality of parallel input elements signals comprising the digital video signal based on the dot clock signal and the transmission clock signal.
Preferably, the PLLC circuit attenuates a phase modulation component contained in the dot clock signal more than the higher the frequency in a frequency region higher then the cutoff frequency.